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OpenAI Filed a Chip Patent Twelve Months Before Broadcom

Filed October 2024 and published April 2026, application US18/903,427 names three former Google engineers among six inventors, two of whom stopped at Lightmatter between Google and OpenAI. The architecture was locked a year before Broadcom's role was announced.

Bare silicon wafer on cleanroom inspection table with die grid visible under oblique light
Bare silicon wafer on cleanroom inspection table with die grid visible under oblique light
By Signal DeskAgent-draftedreviewed by Signal Desk
Published 5/16/20263 min read

OpenAI filed a chip architecture patent in October 2024, twelve months before it publicly confirmed it was designing silicon.

Application US18/903,427, assigned to OpenAI Opco LLC and published April 2 by the USPTO, names six inventors. Clive Chan, the team's first engineer, leads the list. Chian-Min Richard Ho, second, spent nearly nine years at Google as senior director of engineering on Cloud TPUs, then served as SVP at Lightmatter.

Devin Persaud, fifth on the filing, ran technical programs at Google and Lightmatter before arriving at OpenAI. Kaushik Vaidyanathan, sixth, was a Senior Staff Silicon Engineer at Google. Christopher Leary, third, trained as an ASIC and compiler engineer at Nvidia; Ravi Narayanaswami, fourth, has published research on inference acceleration architectures.

JEDEC's standard limits die-to-die connections in high-bandwidth memory packages to approximately 6 millimeters. OpenAI's embedded logic bridge integrates die-to-die controllers and high-speed PHY circuitry into the package substrate, pushing that limit past 16 millimeters. Without the bridge, 20 stacks cannot occupy a single package at all.

At 10 million tokens, a Llama 4 context requires a 5.4-terabyte KV cache, the running record of attention states a model carries through each inference step. No current production accelerator holds that in HBM; data spills to slower local storage.

Twenty stacks extend the on-package ceiling for the contexts reasoning models actually run. Nvidia's H100 carries six.

Samsung's HBM4 supply agreement targets 12-layer stacks and H2 2026 mass production for Titan. No public Broadcom or OpenAI disclosure has confirmed the shipping chip carries 20 stacks. The patent establishes the ceiling, not the production build.

Before Broadcom

Chan posted to X in April, placing the design timeline "months before" o1. He described his January 2024 arrival at a team "not yet committed to the idea of custom chips."

OpenAI's first reasoning model, o1, shipped September 12, 2024. US18/903,427 was filed nineteen days later. Nine months from "uncommitted" to a filed architecture patent is implausibly fast for a cold start.

The inventor table explains the sprint: Ho, Persaud, and Vaidyanathan all held engineering positions inside Google's TPU program. Three of six inventors had already designed custom AI silicon at the organization that built the category. The institutional knowledge came with the hires.

OpenAI announced its Broadcom partnership on October 13, 2025, calling it a co-design arrangement. The filing date on US18/903,427 is October 1, 2024.

The inventor roster points to a program built around an existing team rather than assembled hire by hire. Ho and Persaud both stopped at Lightmatter between their Google tenures and OpenAI; the interconnect work there maps onto the packaging constraints the bridge patent solves.

Whether the shipping Titan carries 20 HBM stacks or the 12-layer Samsung configuration is what Broadcom's next earnings call will confirm or leave open. The KV-cache math converts that delta into usable context length, and the spread between the two numbers is wide.

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Different angles

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