Tech
OpenAI Patent Describes a Chip With 20 HBM Stacks
Application US 2026/0093634, published April 2 and naming Clive Chan as lead inventor, describes a memory architecture with no commercial equivalent. The public story is earbuds. The patent is something else.
On April 2, 2026, the U.S. Patent and Trademark Office published application US 2026/0093634 from OpenAI Opco LLC. The lead inventor listed is Clive Chan. The title is functional: "Non-Adjacent HBM Chiplets, I/O Chiplets, And Compute Chiplets Communicating Via An Embedded Logic Bridge." Chan's LinkedIn describes him as a hardware engineer at OpenAI. There are not many hardware engineers at OpenAI. This patent is the evidence of why that is changing.
The filing solves a specific constraint known as the JEDEC shoreline limit: high-bandwidth memory chiplets can only be placed within approximately six millimeters of a compute die before the signal degrades past usefulness. Nvidia's H100 SXM5 ships with 80 gigabytes of HBM3 within that envelope. The H200 ships with 141 gigabytes of HBM3e. The patent proposes extending the usable placement distance to sixteen millimeters using embedded logic bridges, a technique adapted from Intel's EMIB substrate interconnect architecture. The result, shown in patent diagrams attributed to "Chan; Clive et al," is a compute chiplet surrounded by twenty HBM stacks arranged in double and triple rows around the central die. At current HBM3e densities of 24 gigabytes per stack, that configuration clears 480 gigabytes on a single package.
OpenAI's hardware story, as told in press cycles and earnings calls, is a consumer story. The device it allows coverage to describe is earbuds: a wearable internally codenamed "Sweetpea," confirmed for late 2026, designed by Jony Ive's team, running voice interaction over cloud inference. An April 2026 portfolio analysis of OpenAI's 110 total patents noted the unexpected appearance of G11C (semiconductor memories) and H10B (electronic memory devices) in its CPC classification codes and flagged this as anomalous for a company that has operated as a software provider. US 2026/0093634 explains the anomaly.
The filing is not a research exercise. OpenAI Opco LLC as assignee means the company holds the IP. Industry sources reported in early 2025 that OpenAI was finalizing a custom chip design with Broadcom for a 2026 production run at TSMC. Two weeks before this story published, the Cerebras S-1 filed April 17 disclosed that OpenAI had committed more than $20 billion for 750 megawatts of inference capacity through 2028, with options extending to 2 gigawatts by 2030. The patent describes the upstream architecture. The Cerebras deal is the transitional compute layer while that architecture reaches production.
The inference economics are direct. A chip carrying 480 gigabytes of HBM3e is sufficient to serve a 70-billion parameter model without evicting weights to slower memory tiers. Inference requests of that scale today route across clusters of 16 or more Nvidia accelerators linked by NVLink. Single-chip serving at that parameter count changes the cost structure. It also removes the intermediary.
The embedded logic bridge technique cites Intel's EMIB explicitly as prior art. Patent applicants do not cite prior art for technology they are studying; they cite it for technology they are applying and need to differentiate from. The UCIe-compliant die-to-die interfaces described in the filing mean the architecture accommodates next-generation HBM without a board redesign. That is a platform specification. It is not written for one product cycle.
Sam Altman has said in multiple venues that OpenAI does not want to own hardware. US 2026/0093634 is evidence about what OpenAI is building. Altman's statements are evidence about what OpenAI is choosing to announce.